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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3622 Questions
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  • Answered

    How to debug TF-M ns code on FVP_MPS2_AEMv8M? 0

    • Security
    • TrustZone
    • Armv8-M
    9071 views
    1 reply
    Latest over 7 years ago
    by Tao Lu
  • Answered

    DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts +1

    • Cortex-M7
    • Armv7-M
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    15753 views
    3 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Given an address, how to check its IDAU Security attribution information? 0

    • Architecture
    • Address
    • CHI
    • Security
    • TrustZone
    • Armv8-M
    13242 views
    6 replies
    Latest over 7 years ago
    by Tao Lu
  • Suggested Answer

    M0 Analog-Digital Conversion info needed 0

    • Cortex-M0
    • Cortex-M
    6820 views
    3 replies
    Latest over 7 years ago
    by Sebastian Floss
  • Answered

    How is a signed TF-M image loaded into memory with FVP_MPS2_AEMv8M? 0

    • Layout
    • Address
    • TrustZone
    • Armv8-M
    • Memory
    12237 views
    5 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Suggested Answer

    What happens to upper half of 32-bit data bus when reading 16-bit chip? 0

    • Cortex-M
    • Cortex-M4
    • AHB
    9229 views
    3 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    TRFCR_EL1 register +1

    • CHI
    • Armv8
    4646 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ARMv8 mmu problem +1

    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A
    27961 views
    16 replies
    Latest over 7 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    indirect branches in ARMv8 0

    • Cortex-A53
    • AArch64
    • Armv8-A
    • Cortex-A
    8585 views
    2 replies
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Multi core L1 cache coherent +1

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    7234 views
    3 replies
    Latest over 7 years ago
    by Jorney
  • Answered

    What ARMv8.x revision Cortex-A35 is? 0

    • Cortex-A35
    • Armv8-A
    • Cortex-A
    5362 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Why Cortex-M7 doesn't support bit-banding? 0

    • Cortex-M7
    • Cortex-M
    10931 views
    2 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Suggested Answer

    ARMv8-A CurrentEL Register Definition 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    9979 views
    1 reply
    Latest over 7 years ago
    by kuksho
  • Suggested Answer

    Arm a53: Populate TLB without table walk? 0

    • Cortex-A53
    • Cortex-A
    4421 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    MMU: force identity mapping without pages? 0

    • Cortex-A53
    • Memory Management Unit (MMU)
    • Cortex-A
    14068 views
    14 replies
    Latest over 7 years ago
    by MarkL
  • Not Answered

    The process of initializing ddr and other things on Cortex-A9 0

    • Cortex-A9
    • JTAG
    • Cortex-A
    4034 views
    0 replies
    Started over 7 years ago
    by Dean_Runov
  • Not Answered

    Juno r2 and Xen 0

    • Juno Arm Development Platform
    5378 views
    0 replies
    Started over 7 years ago
    by Fresher
  • Not Answered

    Cortex-A53 Cache protection 0

    • Cortex-A53
    • Cache
    • Cortex-A
    4597 views
    0 replies
    Started over 7 years ago
    by iuli
  • Answered

    Cortex M7 D cache activated without MPU been enabled +1

    • Cortex-M7
    • Cortex-M
    5355 views
    1 reply
    Latest over 7 years ago
    by vishal.s
  • Answered

    single-copy atomicity question for AHB5 0

    • AMBA 5
    • AHB
    8168 views
    2 replies
    Latest over 7 years ago
    by Jacky Chou
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