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Which ARMv8 register controls cache partitioning

rudyjantz
Hi ARM folks,
Which register controls the cache partitioning behavior on ARMv8 chips?
My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning schemes. ThunderX are ARMv8 chips, as mentioned here:
The appropriate manual ought to be this:
In a published paper, another group mentions that they use this feature:
They write:
"To enable SWAP [their prototype], we introduce small changes to the Linux page allocator, and leverage ThunderX’s native architectural support for way partitioning."
And:
"The ThunderX 48-core CMP is an ARM-based processor aimed at the server/datacenter market. It provides the ability to allocate the shared L2 cache by cache ways, up to 16 partitions. ThunderX provides a special register per core, which specifies the cache ways that a core can insert cache lines into. (Cores can still access lines in any cache way.) Once cache ways are assigned to cores (see Section III-B), SWAP configures the per-core registers so that the assignment may be enforced."
I have not, however, been able to find the specific register they're referring to. Thanks in advance for any pointers.
  • 0 Arm Employee Badge

    You'll likely have to check the ThunderX manuals or contact Cavium. The Arm Architecture Reference Manual only describes architectural features (i.e. a contract between software and hardware), and generally attempts to describe the minimal possible requirements.

    Features such as cache partitioning are usually considered micro architectural, and are left up to the processor designers to add and design how they wish.  

    As it happens, this SWAP feature appears to be in a last level cache, which means it might not even be part of the processor, but is actually part of the interconnect or some other part of the SoC.  In this case, it would certainly not be described in the Arm Architecture Reference Manual.