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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3592 Questions
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  • Answered

    How Can I jump from EL1 to EL0 in bare metal environment 0

    • EL1
    • ARMv8 Exception Model
    • EL0
    • Armv8-A
    • Arm64
    25306 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Suggested Answer

    Timer interrupts synchronization in Cortex M4 0

    • Cortex-M4
    • Interrupt
    5107 views
    2 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    Non-secure configuration of UART1 on Arm Musca-A1 0

    • Musca-A
    • TrustZone for Armv8-M
    12651 views
    4 replies
    Latest over 5 years ago
    by Daniel Oliveira
  • Answered

    How long does it take for Cortex A53 to exit low power state? +1

    19909 views
    2 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Optimization of Neon Intrinsics on ARM cortexa53 0

    • Cortex-A53
    • AArch64
    • Optimization Solution
    • GCC
    • NEON
    • Arm Assembly Language (ASM)
    28010 views
    12 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    what's the name of this electronic component? +2

    4695 views
    1 reply
    Latest over 5 years ago
    by Dean03
  • Not Answered

    Problem in understanding behaviour of GCC compiler (aarch64-none-elf-gcc) on Neon intrinsics for ARM cortex a53 0

    • Cortex-A53
    • Optimization Solution
    • GNU Assembler
    • GCC
    • NEON
    • Compilers
    29072 views
    10 replies
    Latest over 5 years ago
    by khan777
  • Answered

    Cortex M0 - Returning from Interrupt 0

    • Cortex-M0
    • Arm Education Media
    10936 views
    13 replies
    Latest over 5 years ago
    by Mezan1
  • Not Answered

    gcc does not generate correct code while building PIC 0

    • GCC
    • Thumb
    • GNU Arm
    • Thumb2
    • Arm Assembly Language (ASM)
    • Cortex-M4
    8031 views
    3 replies
    Latest over 5 years ago
    by a.surati
  • Not Answered

    Setting MPU_RASR for Memory Protection Unit with correct values of TEX/C/B/S bits 0

    4032 views
    1 reply
    Latest over 5 years ago
    by Uma Ramalingam Arm Employee Badge
  • Not Answered

    Cortex M3 System Design - Simulation Environment 0

    4375 views
    2 replies
    Latest over 5 years ago
    by Brixton
  • Not Answered

    uart problem!! 0

    3869 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Abstraction layer for multiple vendors 0

    4140 views
    4 replies
    Latest over 5 years ago
    by pietro
  • Answered

    Cortex M4 and ARM FIR Q15 Hardfault 0

    • Library
    • CMSIS
    • Cortex-M4
    4952 views
    1 reply
    Latest over 5 years ago
    by KoRba
  • Not Answered

    Debugging using DS5 and Foundation model: Interrupt is not forwarded to the CPU. 0

    • AArch64
    • GICv2
    • DS-5 Ultimate Edition
    • Armv8 Foundation Platform
    • DS-5 Technical Support
    23308 views
    4 replies
    Latest over 5 years ago
    by Jorge
  • Not Answered

    arm CC compiler on ARM cortex a53 0

    23486 views
    3 replies
    Latest over 5 years ago
    by khan777
  • Not Answered

    ACE VIP 0

    18970 views
    0 replies
    Started over 5 years ago
    by Enthusiastic learner
  • Not Answered

    Unusual time in booting secondary cores on ARMV8 platform (Zynq MPSoc) 0

    • Power state coordination Interface
    • Armv8-A
    • TrustZone
    21487 views
    2 replies
    Latest over 5 years ago
    by Saud
  • Not Answered

    Hi ARM, Hi ARM, hardfault_handler() 0

    3598 views
    3 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    How to realise a dual-core "LOCK-STEP" Cortex-M7 at the integration level? 0

    7846 views
    2 replies
    Latest over 5 years ago
    by Uma Ramalingam Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
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  • AXI
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  • Cortex-A
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  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
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