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unaligned transfers

tom

Hi all

i have some questions.

Q1

if the master write a burst started in unaligned  address.
How to know the slave support unaligned transfers or not?


Q2
AXI spec mention that  the AXI protocol does not require the slave to take special action based on any alignment
information from the master.
what is the meaning of that?

Thanks a lot

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  • 0 Arm Employee Badge in reply to tom

    Hi Tom,

    In option B I was describing either a 16-beat 8-bit burst (so 0x1 is 8-bit aligned), or a series of different width transactions starting with a 3-beat 8-bit burst (so again 0x1 is 8-bit aligned).

    These would be aligned alternative to perform the original example transfer of 4x4 bytes to address 0x1, which the HW might simply translate into a 5-beat unaligned 32-bit sequence.

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  • 0 Arm Employee Badge in reply to tom

    Hi Tom,

    In option B I was describing either a 16-beat 8-bit burst (so 0x1 is 8-bit aligned), or a series of different width transactions starting with a 3-beat 8-bit burst (so again 0x1 is 8-bit aligned).

    These would be aligned alternative to perform the original example transfer of 4x4 bytes to address 0x1, which the HW might simply translate into a 5-beat unaligned 32-bit sequence.

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