Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    Cortex A9 core locks and cant't stop it +1

    • Debug Tools and Test Methods
    26857 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    Unable to Download Code to Controller 0

    • 5 (BusFault)
    • 3 (HardFault)
    • 6 (UsageFault)
    • Cortex-M4
    12143 views
    11 replies
    Latest over 6 years ago
    by Andy Neil
  • Answered

    How to set secondary core's registers from primary arm? 0

    • Cortex-A15
    • Cortex-A
    40795 views
    12 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"? +1

    • AArch64
    • Armv8-A
    • System MMU
    30556 views
    2 replies
    Latest over 6 years ago
    by Branden Sherrell
  • Answered

    NVIC_EnableIRQ : enables only one interrupt at a time? +1

    25298 views
    22 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    Emissivity value A72 0

    24583 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    SRAM reading problem using FMC at STM32H743. +1

    • Cortex-M7
    5288 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Answered

    Is return stack buffer implemented in Zync 7000 Soc +1

    • Cortex-A9
    • Branch Prediction
    23561 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    ARMv8 memory ordering +1

    • Cortex-A53
    • Armv8-A
    29547 views
    7 replies
    Latest over 6 years ago
    by a.surati
  • Answered

    Is there a built-in ARM assembly instruction for the following problem? +1

    • MDK-Arm
    • Arm Assembly Language (ASM)
    3401 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Answered

    Character recognition using NXP LPC1768 (Cortex-M3) +1

    • Neural Network
    • Cortex-M3
    • Arm NN
    6628 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Calling non-secure Reset Handler from Secure main 0

    • Cortex-M33
    • Armv8-M
    9111 views
    1 reply
    Latest over 6 years ago
    by Radhika Raghavendran
  • Not Answered

    SAU configuration failure 0

    • TrustZone for Armv8-M
    • Cortex-M33
    9214 views
    1 reply
    Latest over 6 years ago
    by Radhika Raghavendran
  • Suggested Answer

    Cortex M0 Vector Table and Bootloading 0

    • Cortex-M0
    • Interrupt Handling
    9020 views
    1 reply
    Latest over 6 years ago
    by Trampas
  • Answered

    Safe exit from HARD FAULT on CortexM0 +1

    • R15 (PC Program Counter)
    • Armv6-M
    • 3 (HardFault)
    14268 views
    9 replies
    Latest over 6 years ago
    by Trampas
  • Answered

    ARMv7M RefMan: What is "Rn" for "MVN"? +1

    • Registers
    • Armv7-M
    • Documentation
    • Thumb2
    3410 views
    2 replies
    Latest over 6 years ago
    by Niklas
  • Answered

    Regarding the J bit 0

    7141 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Rookie needs help +1

    3122 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    COrtex M7 cache hit rate measurement +1

    • Cortex-M7
    • performance
    • Cache Management
    4996 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    How to detect FPU in Cortex M? 0

    • Cortex-M
    4785 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone