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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Not Answered

    Cortex-M MPU User access to privileged code 0

    • Cortex-M
    • Memory Management
    5133 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Setting PC for and waking up secondary cores from the primary core +1

    • Armv8-A
    42957 views
    12 replies
    Latest over 6 years ago
    by jhoney
  • Not Answered

    How to generate an address size fault? 0

    4170 views
    0 replies
    Started over 6 years ago
    by ohskr27
  • Answered

    Unaligned accesses - CMSDK Example Cortex M0 0

    • Cortex-M0
    12702 views
    8 replies
    Latest over 6 years ago
    by eugch
  • Suggested Answer

    M7 data cache and Peripheral DMAs 0

    9041 views
    9 replies
    Latest over 6 years ago
    by Trampas
  • Answered

    Why ARM does not support 64bit for faulting address of IPA? +1

    • ARMv8 Exception Model
    • Armv8-A
    3514 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    uart cortex mo 0

    • Cortex-M0
    2698 views
    0 replies
    Started over 6 years ago
    by gnsh
  • Answered

    The code of app is freertos , the chip has a bootloader, The chip run on Cortex M0 +2

    4201 views
    2 replies
    Latest over 6 years ago
    by hyue
  • Answered

    Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results corrupted stack data abort. Debugger not factor. +1

    28723 views
    5 replies
    Latest over 6 years ago
    by timholt
  • Suggested Answer

    Are there any Cortex-M controller with h.264 encoder? 0

    5146 views
    1 reply
    Latest over 6 years ago
    by Trampas
  • Answered

    Audio mixing efficiently and hard realtime requirment +1

    • algorithms
    • audio
    • Digital Signal Processor (DSP)
    • Cortex-M4
    • STM32 F4
    5130 views
    1 reply
    Latest over 6 years ago
    by Trampas
  • Answered

    How to remap the vector table location? The core of chip is cortex M0 +1

    3152 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    What are the necessary preconditions to load a guest into EL1 from EL2? +1

    • EL1
    • EL2
    • ARMv8 Exception Model
    • Armv8-A
    • Hypervisor
    27149 views
    2 replies
    Latest over 6 years ago
    by MarekBykowski
  • Not Answered

    Cortex-A35 CoreMark results 0

    23071 views
    0 replies
    Started over 6 years ago
    by Etienne Alepins
  • Answered

    custom board based on cortex M0 toggle pins not responding. +1

    • Cortex-M0
    3505 views
    2 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Atomic write (LDAXR/STLXR) causes infinite loop on Cortex-A72 +1

    • Cortex-A72
    • AArch64
    24938 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Bootloader. VTOR, BOOTPROT FUSE, JUMP to app and other related questions +1

    • Cortex-M0
    • Cortex-M
    18964 views
    5 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    What is the top level difference in features between Cortex-M33 and Cortex-M4? 0

    • Cortex-M23
    • Trace
    • ACE
    • AXI
    • CHI
    • Security
    • Cortex-M3
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    • Cortex-M4
    • Internet of Things (IoT)
    • AHB
    • Interrupt
    60010 views
    1 reply
    Latest over 6 years ago
    by bodybeacon
  • Answered

    Fail to connect with CM0DSEvel 0

    • Cortex-M0
    • DesignStart
    6200 views
    5 replies
    Latest over 6 years ago
    by RickyChen
  • Not Answered

    Use DS-5 MPS2_CM33 FVP in non-secure mode ? 0

    9038 views
    0 replies
    Started over 6 years ago
    by ilchang
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