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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3590 Questions
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  • Answered

    Use of WVALID signal in AXI +1

    • AXI
    8368 views
    3 replies
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Disable Cache L1 et L2 Armv8 0

    • Cortex-A72
    • Cache
    • Armv8-A
    15206 views
    8 replies
    Latest over 4 years ago
    by Kael Hong
  • Not Answered

    lpc55s69 over the air update 0

    1619 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    axi problem 0

    9225 views
    6 replies
    Latest over 4 years ago
    by Burns
  • Not Answered

    Corstone SSE-300 FVP simulator 0

    • Cortex-M55
    • Arm Development Studio
    • Corstone SSE-300
    1380 views
    0 replies
    Started over 4 years ago
    by Sap1006
  • Not Answered

    IDE debug Error 0

    1897 views
    3 replies
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Significance of the WVALID signal in AXI 0

    • AMBA
    • AXI
    6726 views
    3 replies
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    I.MX8.MINI(CORTEX A53) Unable to complete the conversion of exception level from EL2 to EL1 0

    3253 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    How to solve a Precise Bus Fault in Cortex -M3? 0

    • Cortex-M3
    4368 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Precise Memory Error 0

    • Cortex-M3
    • Cortex-M
    7728 views
    5 replies
    Latest over 4 years ago
    by Tanushree Bhilare
  • Not Answered

    ARMCM3 startup and linker for qemu-4.2.0 0

    1753 views
    2 replies
    Latest over 4 years ago
    by AbhiSI
  • Not Answered

    [non-Reordering Device memory] Is IMPLEMENTATION DEFINED SIZE set in hardware or in software? 0

    • SoC Implementation
    • AArch64
    • Armv8-A
    • Cortex-A
    • Memory Architecture
    5414 views
    9 replies
    Latest over 4 years ago
    by a.surati
  • Not Answered

    M0 SDK Load Program From SPI Flash 0

    • Cortex-M0/M0+ System Design Kit
    • Cortex-M0
    1314 views
    0 replies
    Started over 4 years ago
    by Gautam-Fermionic
  • Not Answered

    LPC2103 vs. LPC2104 - MAM Bug? 0

    1205 views
    0 replies
    Started over 4 years ago
    by thrust26
  • Not Answered

    Fast integer sign() function on Cortex M4 0

    • Cortex-M4
    1444 views
    0 replies
    Started over 4 years ago
    by MajorMajor
  • Suggested Answer

    Cache coherency in big.little system. 0

    • Cache coherency
    12356 views
    1 reply
    Latest over 4 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    ACE protocol barrier and dvm transactions 0

    4410 views
    2 replies
    Latest over 4 years ago
    by Schultz65
  • Suggested Answer

    ACE protocol cache state 0

    3492 views
    1 reply
    Latest over 4 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    partial cache line store in ACE 0

    3648 views
    1 reply
    Latest over 4 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    ACE protocol Acknowledgement signal 0

    3399 views
    1 reply
    Latest over 4 years ago
    by Christopher Tory Arm Employee Badge
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
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  • AXI
  • Cache
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