Hi Team,We are using TI processor which is based on Cortex R5F Floating Point CPU for our project. Our requirement is to create Undefined Instruction exception for 'Divide by zero' and report same.
To enable the Divide by zero, we have set DZ bit of SCTLR and getting Undefined Instruction exception for divide by zero.
But, while reporting the exception details to user, we are not able to confirm if exception is raised due to 'Divide by zero' occurrence as reading fpscr (DZC bit) returns zero (0).
As per ARM Cortex RM (Cortex-R5 and Cortex-R5F), section 11.5.3 "The exception enable bits in the FPSCR read-as-zero, and cannot be written.",
So is there any way to determine that Undefined Instruction exception is getting raised due to 'Divide by zero' condition ?
Unless there is no other way, you may check the instruction if it is a floating divide and if so "assume" a divide by zero.