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How to know L2 cache ECC single / multiple bit error separately ?

Anderson Chen

For Cortex A53, I can't find separate bit definition for L2 ECC single and multiple bit error in L2MERRSR....

1. bit 31 for L2MERRSR (L2MERRSR_EL1) is for L2 cache ECC multiple bit error, correct ?

2. Which register/bit can I know whether L2 cache ECC single bit error occurs ?

Thanks,

Anderson

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    L2 Cache uses SECDED (single error correction, double error detection), so there is a good chance, that a single bit error won't be counted.

    Edit: The manual says:

    "Error injection on the L2 data RAMs is enabled by setting the L2ACTLR.L2DEIEN bit. While
    this bit is set, double-bit errors are injected on all writes to the L2 cache data RAMs. "

    So,since one cannot test single bit errors, it is likely they are corrected w/o notice.

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  • 0

    L2 Cache uses SECDED (single error correction, double error detection), so there is a good chance, that a single bit error won't be counted.

    Edit: The manual says:

    "Error injection on the L2 data RAMs is enabled by setting the L2ACTLR.L2DEIEN bit. While
    this bit is set, double-bit errors are injected on all writes to the L2 cache data RAMs. "

    So,since one cannot test single bit errors, it is likely they are corrected w/o notice.

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