How to know L2 cache ECC single / multiple bit error separately ?

For Cortex A53, I can't find separate bit definition for L2 ECC single and multiple bit error in L2MERRSR....

1. bit 31 for L2MERRSR (L2MERRSR_EL1) is for L2 cache ECC multiple bit error, correct ?

2. Which register/bit can I know whether L2 cache ECC single bit error occurs ?

Thanks,

Anderson