Cortex-A9-PL310 AXI connection

Hi experts,

I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

I think Figure 1.2 in the TRM is a good starting point:

CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical system configuration

As far as I can see there are two completely distinct AXI interconnect:

1. Processor <-> Cache controller
2. Cache controller <-> L3 memory

The first one is a "point to point" connection. The second instead goes to the real AXI interconnect which, in addition to L3 memory, is connected to other devices/peripherals.

Is my understanding correct?

If so, a more correct figure could be:

Processor <-> Cache controller <-> AXI interconnect <-> L3 memory

Am I right?

Furthermore I would like to know what type of interconnect are these connection AXI3 or AXI4?

Thank you

Regards

Luke