In the TRM of CA53, I see some descriptions of the encodings for AWIDM and ARIDM, and it's quite clear to distinguish Read & Write transactions from different cores.
But in CA72, I can't find such descriptions.
In my simulation, tt seems that it's not able to distinguish normal memory accesses (read or write) according to transaction IDs, even those from different cores may have same IDs.
Can anyone help explain the such transaction-ID related behaviors in CA72.
Thanks a lot ~