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In the section "B14.7.1 Introduction" in IHI0050 - G AMBA® CHI Architecture Specification,
It says "SACTIVE signals must be synchronous to CLK and therefore are not required to be synchronized. If they cross aclock domain, the clock domain crossing bridge is required to synchronize the signals."
I am not sure If It says SACTIVE must be aligned with FLITs or It just has to be synchronous signal which does not consider cycle accuracy thoroughly.
Could you please more elaborate on the meaning of synchronous in the sentence?
Hi there, thanks for asking a question. I have moved your question to the Architectures and Processors forum.