generate an AHB bus matrix ,using the perl script of CMSDK.
Below are the properties of the bus matrix:
When using Modelsim to verify,I found that if i let DMA access ROM while CPU accessing ROM to fetch instruction,there will appear a phenomenon that CPU work normmally,but the timing of DMA AHB interface make mistakes.
I suppose that because of higher priority ,CPU works without disturbing.In contrast,DMA AHB interface goes wrong.
What above is just my thought.I want to know why.