• State Suggested Answer
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 349 subscribers
  • Views 1570 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SError interrupt due to LDAXRB instruction when disable cache on NXP ls1046a

Tony Tu

Hi Experts

My code runs in EL3 on ls1046a RDB in bare mental environment. Here are the focus code after start up.

Step 1: Disable data cache, the the sctlr_el3 is changed from 0x00c5183d to 0x00c51839

Step 2: Update a global variable.

Step 3: do {} while (atomic_flag_test_and_set(&gIRQpRrintmutex));

0000000080005a68: adrp x0, 0x8002e000 <__global_locale+120>
0000000080005a6c: add x0, x0, #0x1b8
0000000080005a70: mov w1, #0x1 // #1
0000000080005a74: ldaxrb w2, [x0]

SError interrupt happened in Step 3: when execute "ldaxrb w2, [x0]" as the resister value as below:

ESR_EL3: 0xbf000002

ELR_EL3: 0x0000000080005a74

If not disable cache as in the step 1, the code execute well.

Any suggestion to fix the SError interrupt?