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Cache coherency in big.little system.

Within an arm system, a cluster is an ACE master connected to the Arm CCI. To keep the cache coherency, the cluster would send some transactions to the bus and are trapped by the snoop filter of CCI.  For example, in Table 7-9 in 7.2.1 of A53 TRM, it says, 

Could someone offer me more details about the error cases, how could those happen? How can a cluster actually evicts some data without sending the evict transactions?

Thank you so much :)