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Are simultaneous accesses to both ITCM and DTCM of Cortex-M7 possible?

Yasuhiko Koumoto

Hi experts and ARM designers,

I have found "ARM® Cortex®-M7 Processor Technical Reference Manual Revision r0p2" on the ARM site. By reading it I have a question. "Figure 1-3 Cortex-M7 functional diagram" shows all TCM accesses go through TCU. Does this mean CPU cannot access both ITCM and DTCM simultaneously? If it is correct, to locate DATA in DTCM is not useful in the performance view point because such accesses cannot be the Harvard Architecture. Is my understanding correct?

Best regards,
Yasuhiko Koumoto.

Parents
  • 0 Arm Employee Badge in reply to Yasuhiko Koumoto

    Hi Yasuhiko,

    Depends on what you mean by simultaneous accesses, the following accesses can happen in parallel:

    -PFU access to I-TCM

    -LSU access to D0/1-TCM

    In the TRM statement you quoted, please note the word "each":

    Each TCM interface receives requests from the LSU, PFU, and AHBS.

    So I-TCM has an arbiter that deal with multiple accesses, and same for D0/1-TCM which has a separated arbiter.

    What you cannot do is

    - PFU (instruction fetch) and LSU (data accesses) both access to I-TCM in the same cycle, or

    - PFU and LSU both access to D0/1-TCM in the same cycle

    regards,

    Joseph

Reply
  • 0 Arm Employee Badge in reply to Yasuhiko Koumoto

    Hi Yasuhiko,

    Depends on what you mean by simultaneous accesses, the following accesses can happen in parallel:

    -PFU access to I-TCM

    -LSU access to D0/1-TCM

    In the TRM statement you quoted, please note the word "each":

    Each TCM interface receives requests from the LSU, PFU, and AHBS.

    So I-TCM has an arbiter that deal with multiple accesses, and same for D0/1-TCM which has a separated arbiter.

    What you cannot do is

    - PFU (instruction fetch) and LSU (data accesses) both access to I-TCM in the same cycle, or

    - PFU and LSU both access to D0/1-TCM in the same cycle

    regards,

    Joseph

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