Looking at the one of the implementations of NVIC_EnableIRQ, Im wondering how the ISER works
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ }
Calling the above two consequitve times with a different IRQn, will erase the enable of the previous interrupt. Does it mean I can enable one interrupt at a time?
NVIC_EnableIRQ(8); // enables IRQ8 NVIC_EnableIRQ(7); // enables IRQ7 but disables IRQ8 ?!?
Correct, or do I miss something?
Further, can I set an IER of a peripheral device without enabling its interrupt ?!?
Thanks in advance !
This chapter is about the ISER, but still no relationship between the ISER and IER...
Again: NVIC => Core, UART => SoC, so read the manual for the SoC you are using.
In the SoC manual, there is no reference about such relationship ...
Do you have an example SoC spec where such relationship is specified ?
STM32F4:
It all is clearly written, but sometimes, not at one place. I suggest getting a copy of "The definitive guide to Arm Cortex-M3 and_cortex_m"
42Bastian Schick said: I suggest getting a copy of "The definitive guide to Arm Cortex-M3 and_cortex_m"
Absolutely!
https://www.elsevier.com/books/the-definitive-guide-to-arm-cortex-m3-and-cortex-m4-processors/yiu/978-0-12-408082-9
You mean the sentence "All interrupts are managed by the NVIC" gives the relationship between the ISER and the IER ?
PS btw is the exert from a SoC manual?
As in every system and SoC I have seen so far in the last 35 years, you have to enable interrupt generation in the peripheral (IER in your case) and in the interrupt controller (NVIC here).
And yes, it is from the SoC manual, hence the "STM32F4" at the top.