Does ARMv8 SOC support cache lockdown?

The ARM Cortex-A57 does not support locking of the L1 or L2 cache, see these pages of the Technical Reference Manual:

ARM Cortex-A57 MPCore Processor Technical Reference Manual: 6.1. About the L1 memory system

ARM Cortex-A57 MPCore Processor Technical Reference Manual: 7.1. About the L2 memory system

As you have supported, support for lockdown is IMP DEF.  So other ARMv8-A implementations might include it.

Hi, since it’s implementation defined, so it really depends on the SoC manufacture. External L2 cache controller does have lockdown registers that you can program, but not for A57.

Why do you think you need to use lockdown/ what are you trying to achieve?

Even if it was supported, it is almost always the wrong answer for A-profile software.

By locking a significant chunk of your cache (1/4 or 1/8 commonly) you reduce the amount of cache available to other applications running. This nearly always results in a slower system on A-profile cores (most A-profile applications have program code size and datasets bigger than the cache), increasing memory bandwidth, and reducing power efficiency.

Pete

hi, George:

Cortex-A57 has an integrated L2 Cache controller, and it does not support cache lockdown feature.

So, it's same with Cortex-A53, right?

And Some ARMv8 SOC may support external L2 Cache controller, so it might support lockdown settings, right?

best wishes,

hi, Peter:

Some firmware could use cache as ram during the boot procedure of power on. Especially for x86 cpu.
So, cache lockdown feature is important for this scene.

hi, Martin:

thanks a lot!

> And Some ARMv8 SOC may support external L2 Cache controller, so it might support lockdown settings, right?

It is possible, but all of the recent Cortex-A family cores have an integrated L2 cache (Cortex-A9 is the only exception I think). It's not a very common feature.

Most ARM SoCs include a small on-chip SRAM for the lowest level firmware to use during boot, which is enough to run the ROM-based bootloader code which initializes the memory controllers to talk to the outside world (e.g., flash and DDR memory) and bootstraps the next level in the boot chain.

As soon as you have that there is no need to run the bootloader from on-chip RAM, you can bootstrap the main firmware and run it from main memory. If you need performance you can even enable the CPU caches, like you would for any other software. This is how common second level firmware loaders, such as U-Boot, work.

Cache lockdown should be unnecessary.

HTH,
Pete

1) Yes

2) yes in theory, but not very common.

hi, Pete:

thanks a lot!

hi, George:

Thanks a lot!

hi, Pete:

Got it!

Thanks a lot!