hi, experts:
In ARMv8 Arch reference manual, it said:
ARMv8 supports cache lockdown feature, but it is implementation defined.
So, my question is:
Has the integrated L2 Cache controller some registers related lockdown feature settings?
I didn't find them in Cortex-A57 TRM.
best wishes,
Why do you think you need to use lockdown/ what are you trying to achieve?
Even if it was supported, it is almost always the wrong answer for A-profile software.
By locking a significant chunk of your cache (1/4 or 1/8 commonly) you reduce the amount of cache available to other applications running. This nearly always results in a slower system on A-profile cores (most A-profile applications have program code size and datasets bigger than the cache), increasing memory bandwidth, and reducing power efficiency.
Pete
hi, Peter:
Some firmware could use cache as ram during the boot procedure of power on. Especially for x86 cpu.So, cache lockdown feature is important for this scene.
Most ARM SoCs include a small on-chip SRAM for the lowest level firmware to use during boot, which is enough to run the ROM-based bootloader code which initializes the memory controllers to talk to the outside world (e.g., flash and DDR memory) and bootstraps the next level in the boot chain.
As soon as you have that there is no need to run the bootloader from on-chip RAM, you can bootstrap the main firmware and run it from main memory. If you need performance you can even enable the CPU caches, like you would for any other software. This is how common second level firmware loaders, such as U-Boot, work.
Cache lockdown should be unnecessary.
HTH, Pete
hi, Pete:
Got it!
Thanks a lot!