hi, experts:
In ARMv8 Arch reference manual, it said:
ARMv8 supports cache lockdown feature, but it is implementation defined.
So, my question is:
Has the integrated L2 Cache controller some registers related lockdown feature settings?
I didn't find them in Cortex-A57 TRM.
best wishes,
> And Some ARMv8 SOC may support external L2 Cache controller, so it might support lockdown settings, right?
It is possible, but all of the recent Cortex-A family cores have an integrated L2 cache (Cortex-A9 is the only exception I think). It's not a very common feature.
hi, Pete:
thanks a lot!