hi, experts:
In ARMv8 Arch reference manual, it said:
ARMv8 supports cache lockdown feature, but it is implementation defined.
So, my question is:
Has the integrated L2 Cache controller some registers related lockdown feature settings?
I didn't find them in Cortex-A57 TRM.
best wishes,
The ARM Cortex-A57 does not support locking of the L1 or L2 cache, see these pages of the Technical Reference Manual:
ARM Cortex-A57 MPCore Processor Technical Reference Manual: 6.1. About the L1 memory system
ARM Cortex-A57 MPCore Processor Technical Reference Manual: 7.1. About the L2 memory system
As you have supported, support for lockdown is IMP DEF. So other ARMv8-A implementations might include it.
hi, Martin:
thanks a lot!