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Of exceptions and aborts..

Felix Varghese
Note: This was originally posted on 21st January 2009 at http://forums.arm.com

The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?
Also, when exactly does the PC get incremented? During the Fetch ?
And exactly when (Fetching / Decoding / Executing) does an exception get generated?
Does an undefined instruction get generated when the instruction is decoded or when it is executed?
What about Data and Prefetch aborts?
  • +1
    Note: This was originally posted on 10th February 2009 at http://forums.arm.com

    The core is ARM7TDMI. Yes, they've given the return instruction for each exception. I was just looking for an explanation for the disparity between them. For some it is MOVS PC,LR, and for some, SUBS PC,LR #4.. I guess 'historical reasons' is the best explanation..
  • 0
    Note: This was originally posted on 9th February 2009 at http://forums.arm.com

    I was wrong about the effect of the instruction, and for some exceptions the instruction will return to the instruction that caused the exception allowing it to be reexecuted.

    Exactly. The value saved in LR seems to be inconsistent across exceptions. Which is the source of all my confusion!
  • 0
    Note: This was originally posted on 29th January 2009 at http://forums.arm.com

    The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?

    Ans:

    SUBS PC,R14, #4 , this instruction is used for debugging. After the execution of this instruction , pc will point to the instruction which caused the exception. Hence one can debug the cause of exception.

    Mov pc, lr is intended to be the last instruction off all the subroutines. Execution of this instruction is similar to a return statement in C.
  • 0
    Note: This was originally posted on 2nd February 2009 at http://forums.arm.com

    LR (R14) will (normally?) point 8 bytes (2 ARM instructions) after the instruction that caused the exception.  If you wish to debug the cause, you'll need to examine LR - 8, not move it to PC using SUBS.


    Link register is used to store return address after a branch with link. As u said  if it holds [address of current instruction + 8 bytes]  ,  how will it return to the next instruction if the previous instruction was a branch with link. All the instructions are 4 bytes aligned.

    Address and corresponding instructions are shown below as an example.
    0x0000_0000:  bl sub_routine1
    0x0000_0004:  add r5, r6
    0x0000_0008:  sub r7, r8

    Value of PC = 0x0000_0008
    Value of LR = 0x0000_0004

    MOV     PC, LR  is intended to be the last instruction in the sub_routine1, which indicates that LR stores the address of the very next instruction.
  • 0
    Note: This was originally posted on 4th February 2009 at http://forums.arm.com

    I was wrong about the effect of the instruction, and for some exceptions the instruction will return to the instruction that caused the exception allowing it to be reexecuted.


    for every exceptions
  • 0
    Note: This was originally posted on 29th January 2009 at http://forums.arm.com

    SUBS PC,R14, #4 , this instruction is used for debugging. After the execution of this instruction , pc will point to the instruction which caused the exception. Hence one can debug the cause of exception.


    LR (R14) will (normally?) point 8 bytes (2 ARM instructions) after the instruction that caused the exception.  If you wish to debug the cause, you'll need to examine LR - 8, not move it to PC using SUBS.

    The above instruction will return to the instruction following the exception so that you can continue execution.  The 'S' on the SUBS in this context will also restore the CPSR from the SPSR so that you would continue as if you'd never taken an exception.
  • 0
    Note: This was originally posted on 2nd February 2009 at http://forums.arm.com

    Link register is used to store return address after a branch with link. As u said  if it holds [address of current instruction + 8 bytes]  ,  how will it return to the next instruction if the previous instruction was a branch with link. All the instructions are 4 bytes aligned.


    My reply was about the "SUBS PC,LR,#4" instruction which is used for returning from exceptions, not "MOV PC,LR", hence the quoted text.  I was wrong about the effect of the instruction, and for some exceptions the instruction will return to the instruction that caused the exception allowing it to be reexecuted.
  • 0
    Note: This was originally posted on 9th February 2009 at http://forums.arm.com

    Exactly. The value saved in LR seems to be inconsistent across exceptions. Which is the source of all my confusion!


    You don't mention the core you are using, but the Technical Reference Manual for the core, I think, will tell you the appropriate instruction to use for each exception.

    The documents can be found at:
    [url="http://infocenter.arm.com/help/index.jsp"]http://infocenter.arm.com/help/index.jsp[/url]
  • 0 Arm Employee Badge
    Note: This was originally posted on 22nd January 2009 at http://forums.arm.com

    The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?

    It is historical.  Due to how very early ARMs were designed, the LR value produced for certain exceptions was always off by a fixed amount.  This was a way of saving gates, at a time when gates were expensive.  The offset has been maintianed ever since for software compatibility.

    Also, when exactly does the PC get incremented? During the Fetch ?

    On an ARM7, the PC points at the instruction being fetched.  So, when in ARM state...

      Instruction being Executed  PC-8
      Instruction being Decoded PC -4
      Instruction being Fetched  PC

    And exactly when (Fetching / Decoding / Executing) does an exception get generated?

    Depends on the exception type.

    Does an undefined instruction get generated when the instruction is decoded or when it is executed?
    What about Data and Prefetch aborts?

    An undefined instruction would be recognised at the decode stage - but would only be taken if it reaches the execute stage.  This is because the preceeding instruction could be a branch (or similar), meaning the undefined instruction would never be executed.

    Similarly, prefetch aborts are detected during fetch.  but only taken if it reaches the execute stage.

    For data aborts the story is more complicated, but it will be during or after the execute stage.