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Of exceptions and aborts..

Felix Varghese
Note: This was originally posted on 21st January 2009 at http://forums.arm.com

The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?
Also, when exactly does the PC get incremented? During the Fetch ?
And exactly when (Fetching / Decoding / Executing) does an exception get generated?
Does an undefined instruction get generated when the instruction is decoded or when it is executed?
What about Data and Prefetch aborts?
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    Note: This was originally posted on 29th January 2009 at http://forums.arm.com

    SUBS PC,R14, #4 , this instruction is used for debugging. After the execution of this instruction , pc will point to the instruction which caused the exception. Hence one can debug the cause of exception.


    LR (R14) will (normally?) point 8 bytes (2 ARM instructions) after the instruction that caused the exception.  If you wish to debug the cause, you'll need to examine LR - 8, not move it to PC using SUBS.

    The above instruction will return to the instruction following the exception so that you can continue execution.  The 'S' on the SUBS in this context will also restore the CPSR from the SPSR so that you would continue as if you'd never taken an exception.
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    Note: This was originally posted on 29th January 2009 at http://forums.arm.com

    SUBS PC,R14, #4 , this instruction is used for debugging. After the execution of this instruction , pc will point to the instruction which caused the exception. Hence one can debug the cause of exception.


    LR (R14) will (normally?) point 8 bytes (2 ARM instructions) after the instruction that caused the exception.  If you wish to debug the cause, you'll need to examine LR - 8, not move it to PC using SUBS.

    The above instruction will return to the instruction following the exception so that you can continue execution.  The 'S' on the SUBS in this context will also restore the CPSR from the SPSR so that you would continue as if you'd never taken an exception.
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