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Of exceptions and aborts..

Felix Varghese
Note: This was originally posted on 21st January 2009 at http://forums.arm.com

The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?
Also, when exactly does the PC get incremented? During the Fetch ?
And exactly when (Fetching / Decoding / Executing) does an exception get generated?
Does an undefined instruction get generated when the instruction is decoded or when it is executed?
What about Data and Prefetch aborts?
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    Note: This was originally posted on 2nd February 2009 at http://forums.arm.com

    LR (R14) will (normally?) point 8 bytes (2 ARM instructions) after the instruction that caused the exception.  If you wish to debug the cause, you'll need to examine LR - 8, not move it to PC using SUBS.


    Link register is used to store return address after a branch with link. As u said  if it holds [address of current instruction + 8 bytes]  ,  how will it return to the next instruction if the previous instruction was a branch with link. All the instructions are 4 bytes aligned.

    Address and corresponding instructions are shown below as an example.
    0x0000_0000:  bl sub_routine1
    0x0000_0004:  add r5, r6
    0x0000_0008:  sub r7, r8

    Value of PC = 0x0000_0008
    Value of LR = 0x0000_0004

    MOV     PC, LR  is intended to be the last instruction in the sub_routine1, which indicates that LR stores the address of the very next instruction.
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  • 0
    Note: This was originally posted on 2nd February 2009 at http://forums.arm.com

    LR (R14) will (normally?) point 8 bytes (2 ARM instructions) after the instruction that caused the exception.  If you wish to debug the cause, you'll need to examine LR - 8, not move it to PC using SUBS.


    Link register is used to store return address after a branch with link. As u said  if it holds [address of current instruction + 8 bytes]  ,  how will it return to the next instruction if the previous instruction was a branch with link. All the instructions are 4 bytes aligned.

    Address and corresponding instructions are shown below as an example.
    0x0000_0000:  bl sub_routine1
    0x0000_0004:  add r5, r6
    0x0000_0008:  sub r7, r8

    Value of PC = 0x0000_0008
    Value of LR = 0x0000_0004

    MOV     PC, LR  is intended to be the last instruction in the sub_routine1, which indicates that LR stores the address of the very next instruction.
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