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Of exceptions and aborts..

Felix Varghese
Note: This was originally posted on 21st January 2009 at http://forums.arm.com

The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?
Also, when exactly does the PC get incremented? During the Fetch ?
And exactly when (Fetching / Decoding / Executing) does an exception get generated?
Does an undefined instruction get generated when the instruction is decoded or when it is executed?
What about Data and Prefetch aborts?
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    Note: This was originally posted on 2nd February 2009 at http://forums.arm.com

    Link register is used to store return address after a branch with link. As u said  if it holds [address of current instruction + 8 bytes]  ,  how will it return to the next instruction if the previous instruction was a branch with link. All the instructions are 4 bytes aligned.


    My reply was about the "SUBS PC,LR,#4" instruction which is used for returning from exceptions, not "MOV PC,LR", hence the quoted text.  I was wrong about the effect of the instruction, and for some exceptions the instruction will return to the instruction that caused the exception allowing it to be reexecuted.
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    Note: This was originally posted on 2nd February 2009 at http://forums.arm.com

    Link register is used to store return address after a branch with link. As u said  if it holds [address of current instruction + 8 bytes]  ,  how will it return to the next instruction if the previous instruction was a branch with link. All the instructions are 4 bytes aligned.


    My reply was about the "SUBS PC,LR,#4" instruction which is used for returning from exceptions, not "MOV PC,LR", hence the quoted text.  I was wrong about the effect of the instruction, and for some exceptions the instruction will return to the instruction that caused the exception allowing it to be reexecuted.
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