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How to force ARM core into debug state when DBGEN was tied LOW?

Note: This was originally posted on 11th January 2009 at http://forums.arm.com

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Hello,

    After our SoC(ARM926EJ-S inside) was mounted on our development board, ARM Multi-ICE was able to connect to it and get its processor ID. But, Multi-ICE could not force ARM core into debug state from Multi-ICE, which means we cannot look at memory, registers, and peripheral status and download new images to execute.

    We found some useful information from Multi-ICE user guide(DUI0048F), ARM926EJ-S (r0p4/r0p5) Technical Reference Manual (DDI0198D), and ARM926EJ (r0p4/r0p5) Integration Manual (DII 0089C). All of them indicated one bug of our hardcore connections, which is the DBGEN should be tied to HIGH for enabling debug functionality. However, our tied the DBGEN to LOW instead.

    Is there any alternative way to re-enable debug functionality in order to force processor into debug state from Multi-ICE when DBGEN was tied to LOW? Thank you in advance for your time.

Regards,
Cuthbert

The following information was we found from documents.

From "ARM926EJ-S (r0p4/r0p5) Technical Reference Manual (DDI0198D)":
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DBGEN / Debug enable /

Input Enables the debug features of the processor. This signal must be tied LOW if debug is not required.
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From "ARM926EJ (r0p4/r0p5) Integration Manual (DII 0089C)":
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DBGEN / Input Debug enable signal

---- Caution ----
If this signal is tied off to logic 0 debugging is not possible.
If you require debug functionality, tie this signal to logic 1 (for example, using RealView ICE).
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Top replies

Peter Harris over 12 years ago +1 verified

Note: This was originally posted on 11th January 2009 at http://forums.arm.com Hi Cuthbert Some SoC designs will provide a implementation-defined mechanism to control the DBGEN signal - this will vary...