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MMU: force identity mapping without pages?

hi,

on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.

I want no memory protection because we manage the whole system ( kind of baremetal processes)

Is there a way to tell the mmu controller that we are in identity mapping for the whole memory available, so that a page walk is not triggered?

thanks

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  • Thank you for the clarification.

    It seems tlb-lockdown can provide some relief, but a53 trm has no mention of it (i.e. it is likely to be unsupported in that processor). 

    The requirements sound very much like an attempt at 'emulating' a MPU through a MMU. The armv7-r trm speaks about PMSA and MPU,  and also describes exactly the conditions that you presented here - identity-map without HW translation table walks.

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  • Thank you for the clarification.

    It seems tlb-lockdown can provide some relief, but a53 trm has no mention of it (i.e. it is likely to be unsupported in that processor). 

    The requirements sound very much like an attempt at 'emulating' a MPU through a MMU. The armv7-r trm speaks about PMSA and MPU,  and also describes exactly the conditions that you presented here - identity-map without HW translation table walks.

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