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hi,
on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.
I want no memory protection because we manage the whole system ( kind of baremetal processes)
Is there a way to tell the mmu controller that we are in identity mapping for the whole memory available, so that a page walk is not triggered?
thanks
Nice. :)
And for the CPU chip, Arm might know if there are any licensees. Wikipedia has a list of them.
Edit: If there are no vendors, does a FPGA solution fare well? I would not know if it is even possible with Arm, but I know Google and certain other companies run (or used to run) their AI processing on custom FPGA solutions.
a fpga would be really cool. My problem with fpga is the price. I need a prototype and then a first batch of 2000 boards. So I guess I am better with something less expensive for a retail price of around 35€..
I was dead wrong. Lattice fpgas are dirt cheap.
There is my take!!! Thank you so much for putting me on the right track. You rock.