hi,
on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.
I want no memory protection because we manage the whole system ( kind of baremetal processes)
Is there a way to tell the mmu controller that we are in identity mapping for the whole memory available, so that a page walk is not triggered?
thanks
I was dead wrong. Lattice fpgas are dirt cheap.
There is my take!!! Thank you so much for putting me on the right track. You rock.