MMU: force identity mapping without pages?

The main problem is the table walk and performance hit involved. I try to find a way around that since everything that will be running will be under control.

Sooner or later we will access an address that won't fit in the TLB because there are memory spread over many pages. The 512 entries won't be enough.

So when the address won't be in the cache, boom, table walk. That is why talking to the TLB might be preferable but apparently impossible. I need a way to tell the system that a table walk is unnecessary. 

Apologies if my point was not clear enough, I really try to work around that problem

The main problem is the table walk and performance hit involved. I try to find a way around that since everything that will be running will be under control.

Sooner or later we will access an address that won't fit in the TLB because there are memory spread over many pages. The 512 entries won't be enough.

So when the address won't be in the cache, boom, table walk. That is why talking to the TLB might be preferable but apparently impossible. I need a way to tell the system that a table walk is unnecessary. 

Apologies if my point was not clear enough, I really try to work around that problem

Thank you for the clarification.

It seems tlb-lockdown can provide some relief, but a53 trm has no mention of it (i.e. it is likely to be unsupported in that processor). 

The requirements sound very much like an attempt at 'emulating' a MPU through a MMU. The armv7-r trm speaks about PMSA and MPU,  and also describes exactly the conditions that you presented here - identity-map without HW translation table walks.

Thanks a lot, so I am out of luck with the armv8 arch..

Oh, I did not mean to say that when I pointed out the armv7-r trm.

Armv8 architecture too provides R and M profiles, which implement MPU (optional on M).

I will look into it right now :)

You were right, I was looking at the wrong cpu family. Cortex R seem like what I was looking for!

Powerful armv8-r (r7 or r8) are a very narrow market though. Could not find vendors implementing them.. sad.

That could be due to the nature of the applications that the R-profile targets.

For e.g., r8 has been targeted at "Highest performance 5G modem and storage". I think that one could find that processor on hard disks, storage arrays, cellphones, or routers, but a board might be hard to come by.

There's "R-Car H3" SoC which contains r7.

Boards containing r4 and r5 are listed by Arm here, while those containing r5 and r7, here.

There are also software models which can be programmed.

Edit: It is likely that even the devices, which a particular CPU targets, might not be implemented yet.

I am actually willing to design my own board.

Now, I should ask a chinese pcba and check if I am lucky :)

Nice. :)

And for the CPU chip, Arm might know if there are any licensees. Wikipedia has a list of them.

Edit: If there are no vendors, does a FPGA solution fare well? I would not know if it is even possible with Arm, but I know Google and certain other companies run (or used to run) their AI processing on custom FPGA solutions.

a fpga would be really cool. My problem with fpga is the price. I need a prototype and then a first batch of 2000 boards. So I guess I am better with something less expensive for a retail price of around 35€..

I was dead wrong. Lattice fpgas are dirt cheap.

There is my take!!! Thank you so much for putting me on the right track. You rock.