A question about interrupt priority degrade

Hi guys,

I found in armv8-arch ref manual that when PRIS bit in the AIRCR is set, the priority of non-secure handler is mapped to the bottom of the priority range. So I did an experiment.

I configured two exceptions, systick and svc. The priority are 2 and 1 respectively.

Then I set the PRIS bit in the AIRCR register in secure world, and called svc in the non-secure world. But I found the secure systick interrupt can't preempt the non-secure svc handler.

I don't know why. Anyone can help? Thanks!

Wenchuan 

Codes are below:

main_s.c:

/*=======================================
* config systick prio 2
*=====================================*/

SysTick_Config(0xff);
NVIC_SetPriority(SysTick_IRQn, 2);
/*=======================================
* config svc prio 1
*=====================================*/
NVIC_SetPriority(SVCall_IRQn, 1);

SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_PRIS_Msk);

main_ns.c

svcall();

void svcall()
{
__asm("SVC 0");
}

non-secure interrupt handler

int flag = 0;

void SVC_Handler(void)
{
volatile int i = 0;
flag = 0;
for(; i < 0xFFFFFFF; i ++);
flag = 1;
}

Parents
  • Hi there,

    SVC and SysTick are banked between security states.

    The code you used to set priority level in Secure world configured the secure SysTick and and SVC priority. Non-secure SVC priority level remains 0.

    You didn't say which processor you are using. Assume you are using Cortex-M23 which have 2 bit priority level:

    Secure SysTick level = (0x02<< 6) = 0x80

    Non-secure SVC = ((0x00 << 6)>>1 | 0x80) = 0x80 (Note: >>1|0x80 is due to PRIS set)

    So both exceptions has the same priority level and cannot preempt each other.

    regards,

    Joseph

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