If SOC is ARMV8-M Mainline.
If a secure world api called within a none-secure world IRQ handler, after enter the secure state, What the mode the CPU is? Handler mode or Thread mode? and if it is handler mode, dose still the MSP is the SP used by CPU.
For example.
1) In none-secure world, issue a SVC call, 2) CPU enter the none-secure world SVC handler, 3) in the SVC handler, call to a secure-world method
4) cpu change to secure state and execute the method being called, at this moment what the CPU mode is, still handler mode or others.
Thanks!
Hi Ed:
Thanks for you reply! Yes, your description is what I'm trying to say.
We are working on an project and want to verify the behavior of the CM33.
What we are doing:
1) Using none secure world SVC software interrupt to change the CPU state to handler mode, within the SVC handler, call to a secure world API, if the CPU state will maintain handler mode after enter the secure state, then we could using the MSP_S and have the privilege to setup PSP_S and PSPLIM_S.
2) If the none secure world call to a secure world API in thread mode, then we could using the PSP_S which has been setup by above step.
Base on your reply, I think the usecase could be implemented without any issues. Please correct me, if I'm wrong.