5 things you might not know about AMBA® 5 CHI

ARM products in server and networking? Yes, it’s happening and AMBA® 5 CHI is a big part of making that happen. The AMBA 5 CHI protocol enables the latest ARMv8 architecture Cortex®-A50 series processors to work together in high-performance, coherent processing hubs of >12 CPUs. But if you have been following the AMBA 5 CHI story at all you probably already knew that. And you might also be familiar with ARM’s system IP products that implement AMBA 5 CHI, the CoreLink™ CCN-504 Cache Coherent Network, recently joined by its big brother the CoreLink CCN-508 and ARM’s latest dynamic memory controller, CoreLink DMC-520.

But what, you ask, is so special about AMBA 5 CHI to enable this? I’ve divided this down in to 5 keys areas:

Network efficency

It’s a protocol designed for the efficient implementation of on-chip interconnect networks. With the emphasis on efficient network, hence the product naming CoreLink CCN-504 where the N stands for Network. A network here means the provision of an implementation-defined topology to pass packets around the SoC. It could be a cross-bar, a ring, a torus, a mesh or another innovative topology. The CCN-504 and CCN-508 topologies are both rings. Efficiency is vital to solve the compute requirements of Big Iron. And ARM is investigating other topologies using AMBA 5 CHI to ensure ARM-class efficiency scales higher and higher.

Seperate transport and payload

AMBA 5 CHI defines a clear separation between the payload and the information needed to transport it to allow a fast (higher frequency, lower latency) and efficient (high wire utilization) transport layer. The clever bit about the packets is that they contain source and destination IDs which allows fast and effective routing of requests and responses.

Free running protocol

CHI is inherently a free-running, non-blocking protocol, designed to avoid deadlocks, livelocks or snarled up packet traffic jams. It has flow control at both the link and the protocol layers, as well as a Quality of Service (QoS) mechanism compatible with that used throughout the CoreLink system IP portfolio.

Cache coherency

The cache coherency protocol builds on AMBA 4 ACE, with innovations in the implementations. CoreLink CCN-504 and CCN-508, for example, both implement L3 caches, distributed to avoid hot-spotting and with snoop directories to reduce unnecessary, energy-consuming snoop traffic. As a natural extension of AMBA 4 ACE, the good news is Verification IP for AMBA 5 CHI is already available from multiple EDA vendors to ensure your design works as it is designed to.

Energy efficiency

ARM, constantly improving its energy efficiency, has ensured CHI provides native support for low power interface states to allow fine granularity of power control in low activity situations.

So AMBA 5 CHI is a key enabler for those building high performance, cache coherent systems with a large and scalable number of processing units and high bandwidth connectivity to I/O and memory, bringing ARM-efficiency to Enterprise markets.


Also, why not take a look at tomconway's blog Why do I need an AMBA 5 CHI Memory Controller?  which describes some of the advantages of AMBA 5 CHI  for memory controllers.