The CoreSight cross-trigger network in a SoC is created from two components: Cross Trigger Matrix (CTM) devices form the backbone of the network and transport events around the SoC; and Cross Trigger Interface (CTI) devices which capture or deliver events to or from other components distributed around the SoC. Although the CoreSight cross trigger network has a variety of potential uses, by far the most common use encountered by DS-5 users is to synchronise cores.
This cross-trigger use-case enables related to cores to enter and exit debug state together. For example, when one core hits a breakpoint and enters debug state, this change in state is picked up by the CTI coupled to that core. The CTI passes the halt event into the cross-trigger matrix, where the CTMs route the event to the CTI coupled to other cores. These CTI issue halt requests to their cores, so that all related cores halt with minimal latency. The debugger doesn’t need to get involved with halting the cores: it just sets up the cross-trigger network so that events are routed correctly. This enables the very low latency which is critical on many SoCs to avoid undesirable effects such as kernel panics.
The ARM DS-5 debugger already supports cross-trigger network configuration and management, and the DS-5 Platform Configuration Editor (PCE) creates the necessary scripting when bringing up a new target platform in the debugger. However PCE currently only supports the most common core topologies: SMP and big.LITTLE. PCE cannot currently create the necessary DTSL scripts for other topologies: for example cross-triggering Cortex-A and Cortex-R/M cores in the same SoC, or halting cores when the on-chip trace buffer fills. These use-cases need custom scripting. DS-5 users can create custom DTSL scripts to drive the DS-5 debugger functionality they need, but there’s a learning curve to be considered. Complex cross-trigger requirements could mean more complexity in DTSL scripts than the average user might be prepared to take on. So in DS-5 v5.25 we’ve revised and enhanced the DTSL functionality around cross-triggering, and added a new DTSL class to make scripting easier and less complex.
These DTSL enhances make it easier and quicker to create custom cross-triggering support in DS-5, backed by groups of custom DSTL controls. This example shows a typical use-case, synchronising the watchdog timer with the Cortex-A57 cores in the ARM Juno reference platform:
In future DS-5 releases we’ll extend the DS-5 PCE to take advantage of this additional DTSL functionality. We’ll also review all the platform configurations that ship with DS-5, to see where DS-5 can leverage these changes to deliver additional value.