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Forums

  • Operating Systems forum

    The latest forum discussions for all Arm technology relating to Operating Systems (OS)
    272 questions
    Cantaff0rd
    UEFI variables from UEFI shell 2 months ago
  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 5 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    707 questions
    Firoz M L
    In CHI how the Slave side is giving the L-Credits to the Master Side 2 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 4 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 9 years ago Arm Employee Badge
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All questions in this Community
  • Answered

    What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean? 0

    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    9481 views
    4 replies
    Latest over 10 years ago
    by Kun.Niu
  • Answered

    Cortex-A series's pipeline is for only one core or for all cores? 0

    • Cortex-A
    • Cortex-A7
    • Cortex-A8
    4670 views
    2 replies
    Latest over 10 years ago
    by Kun.Niu
  • Answered

    Cortex-A7 structure can support max to 4 cores, I want ask the 4 cores have 4 part copy of the registers(37 registers * 4)? 0

    • Cortex-A
    • Cortex-A7
    3749 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Where can I find the docments about how the ARM cortex-A series pipeline works? 0

    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    3294 views
    1 reply
    Latest over 10 years ago
    by daith
  • Not Answered

    Use ITM, How is the input char saved into ITM_RxBuffer? 0

    • Keil MDK
    2349 views
    1 reply
    Latest over 10 years ago
    by Westonsupermare Pier
  • Not Answered

    LPC4337 serial number 0

    • Keil MDK
    842 views
    1 reply
    Latest over 10 years ago
    by Westonsupermare Pier
  • Not Answered

    Issue with .axf with Uvision4 0

    • Keil MDK
    2762 views
    1 reply
    Latest over 10 years ago
    by Gary Olson
  • Answered

    Usage of android GraphicBuffer instead of glReadPixels on SGS3 with Mali 400 MP4 +1

    • Mali-GPU
    • Mali-400
    17124 views
    10 replies
    Latest over 10 years ago
    by Michael McGeagh Arm Employee Badge
  • Answered

    infinite Break Points 0

    • Cortex-M3
    • Cortex-M
    6414 views
    8 replies
    Latest over 10 years ago
    by harshan
  • Not Answered

    reduce output spewed by armlink, i.e., make it silent 0

    • Microcontroller (MCU)
    516 views
    0 replies
    Started over 10 years ago
    by G. Guraaf
  • Answered

    why it apperars an CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST error when read buffer from gpu back to host memory? +1

    • OpenCL
    • Mali-T760
    • Mali-GPU
    11771 views
    8 replies
    Latest over 10 years ago
    by Anthony Barbier Arm Employee Badge
  • Not Answered

    Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore 0

    • Cortex-A9
    • Cortex-A
    4360 views
    2 replies
    Latest over 10 years ago
    by Niranjan Dighe
  • Answered

    In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many? 0

    • Cortex-A
    • Cortex-A7
    4313 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Saving in 8051 IDATA starting from 92H 0

    • Keil C51 Tools
    3148 views
    11 replies
    Latest over 10 years ago
    by Andy Neil
  • Answered

    clean and invalidate cache behavior before same address read +1

    • Cortex-A17
    • Cortex-A
    5690 views
    4 replies
    Latest over 10 years ago
    by loquat
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