Hi all,
I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to NVIC is de-asserted, the handler is called again. At this point I can see that NVIC_ISPR0(interrupt pending register) is 0, but the corresponding bit in NVIC_IABR0(interrupt active register) is set. The handler is called a couple of times more, and after that the pin to NVIC is de-asserted and I can see NVIC_IABR0 is 0 now.
Do I have to manually clear NVIC_IABR0 inside my handler? I think it is a read-only register.
Is there any other way to "acknowledge" this interrupt and tell CPU that I have services it(like reading IACK reg in Cortex A-53)?
Thanks a lot for your help. Please excuse if the question sounds too trivial.
Hello.
as you say, NVIC_IABR0 is a read only register.
I guess you will clear the interrupt source from the peripheral in the interrupt handler.
At the entry point of the handler, NVIC_ISPR0 would be 0, because the activated interrupt would be cleared automatically at the entry point.
However, if your clearing of the interrupt source was delayed, NVIC would accept the same interrupt again.
Therefore you should write NVIC_ICPR0 to clear the 2nd interrupt after clearing the interrupt source.
Does this help you?
Best regards,
Yasuhiko Koumoto.
Hello yasuhikokoumoto. Thanks for your reply.
On entry of the handler, ISPR0(and of course, ICPR0) are 0. So, I don't understand why I need to write into ICPR0 to clear it. Which in itself is strange, because if the pending bit is not re-asserted why is the handler getting called again.
So as to understand correctly, what should be the correct sequence?
- ISR gets called when IABR bit is set by an incoming enabled interrupt.
- On entry into ISR, ISPR is 0 and IABR bit is set.
- In ISR, I clear the interrupt source in peripheral.
- Should I clear, ISPR after this? It is already 0 at this point.
Also, I suspect that pending bit( in ISPR) is never set. Is this expected?
Hello deepakj,
by the way, why do you use IABR?
I think you had better use ISPR rather than IABR because Cortex-M0 and Cortex-M0+ don't include it.
Regarding your confirmation, I think as the following.
Yes.
But I think that first of all ISPR or ICPR is set and the results will reflect to IABR.
Yes, of course.
Probably ISPR is a typo of ICPR.
If it is so, yes.
But, If IABR is 0, you need not to write ICPR.
However, you had better check IABR (or ISPR) before exiting the ISR.
And then, IABR (or ISPR) is not 0, you should write ICPR.
At this time, you had better clear interrupts because the effect of ICPR will be delayed.
For example,
while(ISPR !=0){
clear the interrupt source (if it occurs periodically) and
wrire ICPR.
}
If there is no possibility IABR or ISPR is not 0 at the exit point of the ISR, my suggestion can be ignored.
Your original question is "But before the pin to NVIC is de-asserted, the handler is called again".
Maybe my answer was misdirected.
To solve the original question, it would be rather difficult.
To do so, I think there is no way other than to write ICPR until the ISR will not be called.
The basic background is the same as my answer above.
Hello,
this is an additional information according to my experiment of the real board.
NVIC_IABR seems to hold the active interrupt bits during executing ISR even if the interrupt source had been cleared in the ISR.
And NVIC_IABR seems to be cleared the bits of which interrupt source had been already cleared at the exit point of the ISR.