Hi all,
I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to NVIC is de-asserted, the handler is called again. At this point I can see that NVIC_ISPR0(interrupt pending register) is 0, but the corresponding bit in NVIC_IABR0(interrupt active register) is set. The handler is called a couple of times more, and after that the pin to NVIC is de-asserted and I can see NVIC_IABR0 is 0 now.
Do I have to manually clear NVIC_IABR0 inside my handler? I think it is a read-only register.
Is there any other way to "acknowledge" this interrupt and tell CPU that I have services it(like reading IACK reg in Cortex A-53)?
Thanks a lot for your help. Please excuse if the question sounds too trivial.
Hello,
this is an additional information according to my experiment of the real board.
NVIC_IABR seems to hold the active interrupt bits during executing ISR even if the interrupt source had been cleared in the ISR.
And NVIC_IABR seems to be cleared the bits of which interrupt source had been already cleared at the exit point of the ISR.
Best regards,
Yasuhiko Koumoto.