Hi
i'm using Nucleo board F401RE.
i want to access to ETM with code.
i'm using IAR Embedded Workbench
My code:
#define ETM_CR 0xE0041000 // Address of ETM_CR
#define ETM_LAR 0xE0041FB0 // Address of ETM_LAR
#define UNLOCK 0xC5ACCE55 // Value to unlock the ETM
int main (void)
{
unsigned int *pointer_1 = (unsigned int *) ETM_LAR; // The pointer_1 will point to the address contained in the variable ETM_LAR *pointer_1 = UNLOCK; // Cheque UNLOCK to the contents of the memory address ETM_LAR
unsigned int *pointer_2 = (unsigned int *) ETM_CR; // The pointer_2 will point to the address contained in the variable ETM_CR
unsigned int var = 0x0; // I initialize a variable called var
var = *pointer_1; // I assign the contents of pointer_1 to the variable var
while (1) { printf("Il contenuto in esadecimale è: %p\n", *pointer_1); // I expect to see on the terminal the value of UNLOCK }
}
Hi Lorenzo,
Whilst the Cortex-M3 TRM shows ETMLAR to be WR, the CoreSight Architecture spec says this register is WO. When I try to read that register in a Cortex-M4 (sorry I dont have an M3 handy) I get 0. I would suggest you read the ETMLSR (located at 0xE0041FB4) to indicate the success of you unlocking the registers.
Using the ArmDS Debugger on my Cortex-M4:
x/w 0xE0041FB40xE0041FB4: 0x00000003memory set 0xE0041FB0 32 0xC5ACCE55x/w 0xE0041FB40xE0041FB4: 0x00000001
The change of bit 1 of 0xE0041FB4 from 1 -> 0 shows that the registers are now accessible.
Does that help?
Regards Tony
Hi Tony and thanks for the reply
My board is Cortex M4
What do you thing about the settings of tool IAR shown in the image ?
Thanks
I'm not using a kit debugger
Sorry Lorenzo, but I have no experience using the IAR tools. Everything you show in the image looks reasonable to me. Was there something specific you were concerned about?
If you wish to share more about what you are trying to achieve, or ask something more specific to Cortex-M4, I can try to help.
Maybe others on this forum know more about IAR tools.
I would like to access the ETM logs and keep track of the data in it without using an external debugging kit, then only through code.
In any case if you know a different tool I can use it quietly another. I have no constraint in this respect.
I took a look at https://www.st.com/en/evaluation-tools/nucleo-f401re.html is this your board?
If it is, this board uses the LQFP64 package. Looking at the SoC data sheet (https://www.st.com/resource/en/datasheet/stm32f401re.pdf) only the UFBGA100 package presents the TRACECLK, TRACED[0..3] to the outside world.
The ETM watches what the core is doing and converts its execution history into a compressed trace data stream which it then has to send somewhere. Two common options are:
The ST design only provides the second option and the SoC package on your board does not bring these pins out. So I dont think it is possible for you to make use of the ETM to look at execution history - which I presume is the 'ETM logs' you are referring to. In any case, you would always need an external trace capture device - you cant view the ETM output 'in your code'.
What the ST device (and package) does have, is SWO output (sometimes called SWV). I suggest you take a look at https://www.st.com/resource/en/application_note/dm00354244.pdf and see if using printf style output in your code can help with the problem you are trying to address.
This is my board
Anyway I don't care about having traceclk, TRACED [0.. 3] Being that I don't have to use any external debugging kits, right?
Yes, thats right - its just that those pins are the only way you can capture the ETM output. So as I said, I dont see how you can make any use of the ETM for execution history trace.
Ok But if I also want to set the bits of the registers of ETM, is it correct to write in them through the use of pointers? As I wrote in the code of my first message?
Thank you
I dont have access to the IAR compiler, so I can only give you generic guidance. Its also a while since I programmed in C ;-)
Other than that your code looks good to me as a way of accessing the ETM registers.