How can I debug two A53 cores in DS-5 tool

Dear all,

I want to debug our Soc chip with DS-5 tool, the SoC has two Cortex-A53 cores.
When I debug Bare-metal code in DS-5, I only can debug one of two A53 with Bare-metal code ,
Any one of two A53 can run exactly. When I debug two A53 at the same time, it don't work normally.

// -----------------------------------------------------------------------------
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//  only be used by a person authorised under and to the extent permitted
//  by a subsisting licensing agreement from ARM Limited or its affiliates.
//
//             (C) COPYRIGHT 2014-2016 ARM Limited or its affiliates.
//                 ALL RIGHTS RESERVED
//
//  This entire notice must be reproduced on all copies of this file
//  and copies of this file may only be made by a person if such person is
//  permitted to do so under the terms of a subsisting license agreement
//  from ARM Limited or its affiliates.
//
//       SVN Information
//
//       Checked In          : $Date: $
//
//       Revision            : $Revision: $
//
//       Release Information : CoreSight-SoC-TM100-r3p2-00rel1
//
// -----------------------------------------------------------------------------
        .section boot, "ax", %progbits
        .global  bootcode

// -----------------------------------------------------------------------------
// Generic boot code
// -----------------------------------------------------------------------------
bootcode:
// -----------------------------------------------------------------------------
// Initialise register bank
// -----------------------------------------------------------------------------
                mov     x0, xzr
                mov     x1, xzr
                mov     x2, xzr
                mov     x3, xzr
                mov     x4, xzr
                mov     x5, xzr
                mov     x6, xzr
                mov     x7, xzr
                mov     x8, xzr
                mov     x9, xzr
                mov     x10, xzr
                mov     x11, xzr
                mov     x12, xzr
                mov     x13, xzr
                mov     x14, xzr
                mov     x15, xzr
                mov     x16, xzr
                mov     x17, xzr
                mov     x18, xzr
                mov     x19, xzr
                mov     x20, xzr
                mov     x21, xzr
                mov     x22, xzr
                mov     x23, xzr
                mov     x24, xzr
                mov     x25, xzr
                mov     x26, xzr
                mov     x27, xzr
                mov     x28, xzr
                mov     x29, xzr
                mov     x30, xzr
// Zero the stack pointers, link registers and status registers
                mov     sp,       x0
                msr     sp_el0,   x0
                msr     sp_el1,   x0
                msr     sp_el2,   x0
                msr     elr_el1,  x0
                msr     elr_el2,  x0
                msr     elr_el3,  x0
                msr     spsr_el1, x0
                msr     spsr_el2, x0
                msr     spsr_el3, x0
// Initialise vector base address register for EL3
                adr     x1, vector_table
                msr     vbar_el3, x1
// -----------------------------------------------------------------------------
// Variable definitions
// -----------------------------------------------------------------------------
// Values to set I and F bits in cpsr register
.equ I_BIT                   , 0x80
.equ F_BIT                   , 0x40
// Values for different modes in cpsr register
.equ MODE_IRQ                , 0x12
.equ MODE_ABT                , 0x17
.equ MODE_UND                , 0x1b
.equ MODE_SYS                , 0x1f
// -----------------------------------------------------------------------------
// Initialise stack pointers
// -----------------------------------------------------------------------------
// Use CPU number to calculate stack pointer
                adr     x1, stack_top
//  ldr x1, =stack_top
                mrs     x2, mpidr_el1
                and     x2, x2, #0xFF     // x2 == CPU number
                mov     x3, #CPU_STACK_SIZE
                mul     x3, x2, x3
                mrs     x2, mpidr_el1
                and     x2, x2, #0xFF00
                asr     x2, x2, #8        // x2 == Cluster number
                mov     x4, #(CLUSTER_STACK_SIZE)
                mul     x2, x4, x2                // 4stack_size x clusternum
                add     x3, x3, x2                // add 4 X cluster num x stack size
                sub     x1, x1, x3
                mov     sp, x1
// -----------------------------------------------------------------------------
// NEON
// -----------------------------------------------------------------------------
#ifdef NEON
// This conditional code is controlled by the Makefile. Define NEON if the compiler supports it.
// Enable NEON and initialize the register bank if NEON is present
                mrs     x0, ID_AA64PFR0_EL1
                ubfx    x0, x0, #16, #4  // Extract the floating-point field (x0 == 0x0 if present)
                cbnz    x0, neon_end     // Skip FP initialization if not present
                mov     x1, #(0x3 << 20)
                msr     cpacr_el1, x1
                mov     x1, #(0x3 << 20)
                msr     cpacr_el1, x1
                isb
                MRS x0,CPTR_EL2
                LDR x1,=0x400
                BIC x0,x0,x1
                MSR CPTR_EL2,x0
                ISB
                MRS x0,CPTR_EL3
                LDR x1,=0x400
                BIC x0,x0,x1
                MSR CPTR_EL3,x0
                ISB
                fmov    d0,  xzr
                fmov    d1,  xzr
                fmov    d2,  xzr
                fmov    d3,  xzr
                fmov    d4,  xzr
                fmov    d5,  xzr
                fmov    d6,  xzr
                fmov    d7,  xzr
                fmov    d8,  xzr
                fmov    d9,  xzr
                fmov    d10, xzr
                fmov    d11, xzr
                fmov    d12, xzr
                fmov    d13, xzr
                fmov    d14, xzr
                fmov    d15, xzr
                fmov    d16, xzr
                fmov    d17, xzr
                fmov    d18, xzr
                fmov    d19, xzr
                fmov    d20, xzr
                fmov    d21, xzr
                fmov    d22, xzr
                fmov    d23, xzr
                fmov    d24, xzr
                fmov    d25, xzr
                fmov    d26, xzr
                fmov    d27, xzr
                fmov    d28, xzr
                fmov    d29, xzr
                fmov    d30, xzr
                fmov    d31, xzr
neon_end:
#endif
// -----------------------------------------------------------------------------
// Setup MMU and TLBS
// -----------------------------------------------------------------------------
// MMU ifdef defined in makefile
#ifdef MMU
ttb_setup:
                //  Create page tables
                adr     x0, ttb0_base
                msr     ttbr0_el3, x0
                ldr     w1, =0x80803520
                msr     TCR_EL3, x1
                ldr     x1, mair_value
                msr     MAIR_EL3, x1
//               Enable caches and MMU
                mrs     x0, sctlr_el3
                orr     x0, x0, #(0x1 << 2)   // C bit (data cache)
                orr     x0, x0, #(0x1 << 12)  // I bit (instruction cache)
                orr     x0, x0, #0x1          // M bit (MMU)
                msr     sctlr_el3, x0
#endif
// -----------------------------------------------------------------------------
// Ensure all writes to system registers have taken place
// -----------------------------------------------------------------------------
                dsb sy
                isb sy
// -----------------------------------------------------------------------------
// Enable interrupts
// -----------------------------------------------------------------------------
                msr     DAIFClr, #0xF
//               Configure FIQ to be taken at EL3 by setting SCR.FIQ.
//               This allows a FIQ to wake CPUs that wait in WFI in EL3
//               at the end of the boot code.
                mrs     x0, scr_el3
                orr     x0, x0, #(1<<2)// FIQ bit
                orr     x0, x0, #(1<<1)// IRQ bit
                msr     scr_el3, x0
// -----------------------------------------------------------------------------
// Start the test
// -----------------------------------------------------------------------------
cpu_start:
// SelectCPU is run first so that only the selected CPU will run initialisation.
// The cpu selection could instead be done here to fit the requirements of specific systems
// For gcc we need to call init_libc to handle initialisation of c libraries etc. before starting main
// Once main has returned _exit will finish the simulation using the function specified in gcc_retarget.c
                bl SelectCPU
                bl init_libc
                bl main
                b _exit
        .end
// Called from SelectCPU
void init_libc(void)
{
    // Zero the BSS
    size_t bss_size = __bss_end__ - __bss_start__;
    memset(__bss_start__, 0, bss_size);
    atexit(__libc_fini_array);
    __libc_init_array();
}
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