What are coherent observers?

ARMv8 reference manual refers to "coherent observers" to define coherence-order (pg B2-117).  Which observers are coherent?

  • This probably not the best part of the forum to post this question in, I'd suggest "Cortex-A / A-Profile forum" might be better.

    Anyway, so there's a couple of ways to answer the question.  Starting with the definitions (take from the Arm ARM's glossary):

    A PE or mechanism in the system, such as a peripheral device, that can generate reads from or writes to memory.|

    Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte in memory by the members of that set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all to writes to that memory location is the coherence order for that byte in memory

    So strictly, a "coherent observer" is any observer whose accesses are coherent.

    Ok, I get that's this is probably not a very helpful answer.

    Observer means anything that can make accesses to memory.  So for example, a PE (aka the core) is classed as being multiple observers.  There's the instruction fetcher, the data fetcher and the MMU table walker.  These are classed as each being separate observers. If you have a multi-core processor, then the same is true for each individual core within the processor.  Observer also covers other masters in the system, such as DMA controllers or GPUs.

    Coherent here roughly means those things that are part of the cache coherency mechanism.

    So a "coherent observer" is anything that can access memory and is using the cache coherency logic.

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