How to get the pipelines stages of the thunderX2 vulcan Micro-architecture like in the classic RISC 5 stages with the corresponding stages names?

Hi all,

I am working on ARM Marvell ThunderX2 vulcan micro-architecture and want to understand it pipelines stages names.

As the classic RISC pipeline has 5 stages (named Fetch, Decode, Memory, Execute, Write-Back) i want to know the corresponding names for each of the 15 stages of ThunderX2 pipeline.

Thanks.

More questions in this forum