Help with AXI4 payload with data bus width of 32 bits

Hello All, I am referring to the ARM AMBA TLM 2.0 guide. I am trying to send around 50KB of data through AXI4 protocol. Here it uses the AXI4 payload and not the generic payload. My data bus width is 32 bits. 1 data beat would mean 4 bytes so I can send 2 data beats in a single transfer. I wanted help with as to how many payloads I need to construct to send over this data. Let me know if you need any additional info to help reconstruct this. 

WDATA: 32 bits

AWADDR: 32 bits

ARSIZE[2:0]

ARLEN[3:0]

  • I can't help answer this question from a TLM perspective, but from an AXI protocol perspective I could suggest the following.

    Firstly with a 32-bit data bus this means you can transfer 4 bytes (each byte is 8-bits) in each transfer on the WDATA or RDATA buses.

    AXI4 added support for INCR bursts of up to 256 transfers (AXI3 limited it to 16 transfers), so the maximum data a single AXI4 transaction can transfer is 256x4 bytes, so 1024 bytes.

    So if you want to transfer "around 50KB of data", this would suggest you would need to create around 50 AXI transactions.

    But I'm not sure how this translates into TLM terminology. Can't help you there.

    Note that the signals you listed (WDATA, AWADDR, ARSIZE and ARLEN) are a mix of signals from read and write transactions, so it isn't clear if you are referring to read or write operations (not that it affects the answer I gave). 

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