I have an AXI master and an AXI slave connected to interconnect in my setup.
I have used AMBA Designer tool to generate Interconnect RTL.
I have a question on Tidemark :
What is the significance of Tidemark in AXI interconnect?
Why Tidemark option is included for both master and slave interfaces?
Could you please explain when Tidemark is set to some non zero value, how does AWREADY signal behaves at master end ?
At slave interface block (master end) of interconnect , I had set tidemark =4 . I am performing back to back outstanding transactions , AWREADY signal at master end behaves as shown in the attached picture. Why AWREADY is behaving in this way?
From the NIC-301 TRM:
Data release mechanism
When you configure a write data FIFO of at least 4, you can also set an additional write tidemark function, named wr_tidemark. This is a tidemark level that stalls the release of the transaction until:
• The network receives the WLAST beat.
• The write FIFO becomes full.
• The number of occupied slots in the write data FIFO exceeds the write tidemark.
For more detailed support, you would need to contact Arm Support.
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