(#context): I have a Cortex-R52 in the SoC design. My team is in charge of FPGA prototyping of the entire/part of the SoC. I am prototyping (on FPGA) part of the SoC which has the R52 plus some other IPs.
(#problem): It's not possible to close timing for FPGA with all the clock gates inside R52 enabled. As there are too many layers of BUFGCEs which cause severe clock skew, and that cannot be fixed in placement and routing.
(#question): Can I change the clock gate cells (just for FPGA) and tie the output directly to the input (e.g. assign clk_out = clk_in), and it will NOT impact the functionality of Cortex-R52? In FPGA prototyping we do not care any functionality related to power.