1. How barrier instructions like `dmb ishld` and `ldar/stlr` translate to ACE barrier transactions?
I am curious about how barrier instructions which will only affect specific types of memory operations would translate to ACE barrier transactions.
I supposed that the load/store operations which will not be affected by that barrier would translate into transactions which ignore the barrier (Axbar = 0b10)?
2. As described in ARM AMBA Manuel, the requirement of not stalling the barrier transaction is that "All transactions before the read barrier and write barrier have been snooped as required, and all write transactions that must be before the barrier have been issued".
Does it mean that only after the responses of the snoop transactions for all load/store operations before that barrier has been received, the corresponding barrier transaction can be issued downstream, or the corresponding response for that barrier transaction can be send.
Thanks in advance!