Hi,
I have a question.
when a processor sends a clean request to data cache, how data cache should behave?
1. does it need to evict all cache lines present in cache (including clean lines) or does it evict only Dirty lines.
2. if dirty lines to write back to upper level only, then does these dirty lines can we retain by changing its state to clean in cache itself?
My other question is if in cache coherency, one processor sends flush request then cache lines present inside victim cache will be written back to upper level but how to inform snoop filter that cache has invalidated all cache lines present in it??
do we need to raise any transaction for flush request from processor??
KPranav said:when a processor sends a clean request to data cache, how data cache should behave?1. does it need to evict all cache lines present in cache (including clean lines) or does it evict only Dirty lines.
A Clean operation without invalidate (such as DC CSW or DC CVAU) is only required to write dirty lines back to the point specified by the instruction. It's not required to evict any lines from the cache.
A Clean and Invalidate is required to both write back dirty lines and to invalidate/evict all specified copies of that line.
KPranav said:2. if dirty lines to write back to upper level only, then does these dirty lines can we retain by changing its state to clean in cache itself?
For a Clean operation, yes, you're only required to ensure that the dirty data reaches the point in the system specified by the Clean operation - for example the Point of Unification or Point of Coherency. The lines can remain in the cache.
KPranav said:
ACE and CHI both have an Evict transaction type, which is a message to the interconnect that a Clean line has been evicted. This is only required for performance, as a snoop to a cache that does not have the line simply results in the miss, which is functionally fine.