What is the top level difference in features between Cortex-M33 and Cortex-M4?

This is a very common question.

The diagram below is a pictorial description of the differences followed by some explanations.

Cortex-M33 v Cortex-M4 features

Starting from the bottom:

  • Cortex-M33 is an implementation of the ARMv8-M architecture. Full details are in my blog on the 5 key features of the Cortex-M33
  • Using the same debug interface as the other Cortex-M processors
  • Offering the same functionality of a wake up interrupt controller for low power operation 
  • Implementing the same DSP/SMD instructions as the Cortex-M4
  • Implementing the latest FPU specification which adds more instructions beyond what Cortex-M4 has
  • Using the AHB5 specification for the system and memory interface to extend security to the whole system
  • Using the latest version of the memory protection specification to simply the setup of regions
  • Extends the number of maximum interrupts to 480
  • An updated embedded trace macro cell to fit the processor design
  • A micro trace buffer as an option to trace into memory instead of out to the trace interface
  • Updated debug components that enhance debug operations and simplify usage
  • A co-processor interface that supports up to 8 co-processors
  • Stack limit checking in hardware
  • TrustZone for software and hardware isolation 

All the features are configurable and optional.

In case you have not found it yet, there is a white paper with technical details on Cortex-M23 and Cortex-M33 processor.

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