The Peripherals memory map of FVP_BaseR_Cortex-R52x1


I am trying to do some PoC on FVP_BaseR_Cortex-R52x1. My code can boot from EL2 and enter to EL1 properly. But when I was trying to access PL011 UART0, I got a DATA Abort. From the  Fast Models Reference Manual Version 11.4.2, I found the PL011 UART0 base is 0xB0090000 and some sample code for FastModel is using 0x1C090000 as A-series. But I had verified, 0x1C090000 of  FVP_BaseR_Cortex-R52x1 is a DRAM memory address. Is there any correct Peripherals memory map for  FVP_BaseR_Cortex-R52x1?


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