I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me:
Determines if instructions can be cached at any available cache level:0 = instruction caching disabled at all levels. This is the reset value.1 = instruction caching enabled.
Does "instruction caching disabled at all levels" mean that PFU is disabled? I would guess not, because the TRM says "The PFU obtains instructions from the instruction cache, the TCMs, or from external memory".
If SCR bit 12 doesn't disable PFU, what's the proper way to completely disable instruction pre-fetch?
Taking a step back, what are you trying to achieve? Why do you want to disable prefetching?
The processor will always do some degree of prefetching, it has to in order to feed the pipeline. SCTLR.I only controls caching of instruction fetches, not pre-fetching more generally.
Thanks for the info. Suppose my application nominally executes out of flash. Flash diagnostic require that flash be completely idle during the diagnostic test. So, I might decide to execute the diagnostic routine out of RAM, when the routine completes I'll jump back to flash. If I don't disable PFU, then unwanted flash accesses can occur during the final N instructions of my diagnostic routine (where N is the effective PFU FIFO depth) when PFU follows the return instruction and starts pre-fetching from flash.
If PFU can't be disabled, one simple solution is to pad the end of my routine with N NOPs. Any better ideas?
Padding with NOPs sounds like the best solution. Make sure to disable interrupt ;-)
I'd suggest using the MPU. Before starting the test, mark the flash as execute (or no access, if the test doesn't involve direct access by the processor). Then after the test is complete, re-enable execution/access. The processor won't prefetch instructions from a region without execution permissions.