Disabling PFU / instruction pre-fetch on Cortex-R4?


I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me:

Determines if instructions can be cached at any available cache level:
0 = instruction caching disabled at all levels. This is the reset value.
1 = instruction caching enabled.

Does "instruction caching disabled at all levels" mean that PFU is disabled? I would guess not, because the TRM says "The PFU obtains instructions from the instruction cache, the TCMs, or from external memory".

If SCR bit 12 doesn't disable PFU, what's the proper way to completely disable instruction pre-fetch?